As noted previously, the following table reflects my plan to support: |
-------------------------------------------------------------- Port Register DB25 Port Name VNA Line Name Type Offset(1) Bit(2) ----- ---------- ----------------- ---- --------- -------- + 1 Strobe* Test Set Sw(2 rx) Out 2 n0 2 D0 RF DDS Data Out 0 0 2 D0 DET1 SDI Out 0 0 2 D0 DET2 SDI Out 0 0 3 D1 LO DDS Data Out 0 1 4 D2 DDS W_CLK Out 0 2 5 D3 DDS FQ_UD Out 0 3 6 D4 DDS Reset Out 0 4 7 D5 DET1 SCK Out 0 5 7 D5 DET2 SCK Out 0 5 8 D6 DET1 nCS(4) Out 0 6 9 D7 DET2 nCS(4) Out 0 7 10 ACK* Unused In 1 6 11 BUSY DET1 nSDO(4) In 1 n7 12 PError DET2 nSDO(4) In 1 5 +13 Select VNA Present(5) In 1 4 +14 AUTOFD* Atten0 Out 2 n1 15 FAULT* Unused In 1 3 16 INIT* Atten1 Out 2 2 17 SelectIn* Atten2 Out 2 n3 18 Ground Ground 19 Ground Ground 20 Ground Ground 21 Ground Ground 22 Ground Ground 23 Ground Ground 24 Ground Ground +25 Ground Ground (1) Offset Register ------ -------- 0 Data 1 Status 2 Control (2) "n" in this column only signifies that the parallel port line is inverted from the register bit. (3) "+" are DB-25 end pins (4) Note that assignment of a particular PCB's ADC is totally controlled by which DB25 pins are used for its nCS and its nSDO. This permits the PCBs to be built identically with respect to the ADC, assuming the fast (or the slow) ADC is on both PCBs. (5) This is +5 Vdc, used for the DDSs, thru a series 1 kohm resistor for current limiting on the parallel port. It is intended to be used by software as one way to determine if the VNA is present on the parallel port and powered up. -------------------------------------------------------------- The designation of pins as "Unused" is not intended to preclude
their future use for some yet to be defined feature or function. They
are not "reserved" as there are no plans to use them at this point,
but it possible that one or more may get used if a problem arises in
the 2nd detector beta test. |
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Please feel free to contact me with any comments or questions
at:
73,
Paul Kiciak, N2PK